supertex inc. supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com hv739 features hvcmos technology for high performance high density integration ultrasound transmitter bipolar 100v or unipolar 0 to 200v output voltage 3.0a source and sink peak current up to 10mhz operation frequency matched delay times 1.8v to 5.0v cmos logic interface over temperature sensing under voltage protections applications ndt ultrasound equi pment piezoelectric transducer drivers sonar, ranger and ?o w metering ? ? ? ? ? ? ? ? ? ? ? ? general description the supertex hv739 is a single channel mon olithic 200v 3.0a high-speed pulser. it is designed for ndt and medical ultrasound applications. this high voltage and high-current integrated circuit can also be used for other piezoelectric, capacitive or mems sensor in ultrasonic transducer and sonar ranger applications. hv739 consists of controller logic interface circuit, voltage level translators, mosfet gate drives and high current power p-channel and n-channel power mosfets as the output stage. the output stage of hv739 is designed to provide output peak currents over 3.3a with up to 200v swing. the p- and n- channel power fets gate drivers are supplied by two ?oating 10 to 12vdc power supplies referenced to v pp and v nn . this direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the pcb layout easier. typical application circuit high speed 100v 3.0a ultrasound pulser nin sub +88 v vpf vdd +12v gref +1.8 to 5.0v logic inpu t vpp +100 v en v pp v nn pin c1 vnn -100 v txn -88 v c2 c3 c5 c4 txp hv out 1 x1 r1 d1 d2 vnf vsub vll +1.8~5v +100 v c6 c7 en_pwr otp over temp. vss p-drive r n-drive r hv739 level translator level translator ????????
2 hv739 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com ordering information device package option 32-lead qfn 5.00x5.00mm body 1.00mm height (max) 0.50mm pitch hv739 HV739K6-G -g indicates package is rohs compliant (green) absolute maximum ratings parameter value v ss , power supply reference 0v v ll , positive logic supply -0.5v to +7v v dd , positive logic and level translator supply -0.5v to +14v (v pp -v pf ) positive ?oating gate drive supply -0.5v to +14v (v nf - v nn ) negative gate ?oating drive supply -0.5v to +14v (v pp -v nn ) differential high voltage supply -0.5v to +220v v pp , high voltage positive supply -0.5v to +220v v nn , high voltage negative supply -220v to +0.5v all logic input pin, nin and en pin voltages -0.5v to +7.0v otp, over temperature protection output -0.5v to +7.0v (v sub - v ss ) substrate to v ss voltage difference +220v (v pp -txp x ) v pp to txp x voltage difference +220v (v sub - txp x ) substrate to txp x voltage difference +220v (txn x -v nn ) txn x to v nn voltage difference +220v storage temperature -65c to 150c thermal resistance, ja (4-layer,1oz, 4x3in. 9-via pcb) 25c/w absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. power-up sequence step description 1 v sub 2 v ll with logic signal low 3 v dd 4 v pf and v nf 5 v pp and v nn 6 logic control signals power-down sequence step description 1 all logic signals go to low 2 v pp and v nn 3 v pf and v nf 4 v dd 5 v ll 6 v sub pin con?guration package marking 32-lead qfn 1 32 hv739 llllll yyww aaaccc l = lot number yy = year sealed ww = week sealed a = assembler id c = country of origin = green packaging 32-lead qfn (k6) (top view) package may or may not include the following marks: si or ????????
3 hv739 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com dc electrical characteristics (operating conditions, unless otherwise speci?ed, v ss = 0v,v ll = +3.3v, v dd = +12v, v pp -v pf = +12v, v nn -v nf = -12v, v pp = +100v, v nn = -100v,t a = 25c) output p-channel mosfet, txp sym parameter min typ max units conditions i out output saturation current 3.0 3.3 - a 1.0 load to ground r on channel resistance - 6.9 - i sd = 500ma c oss output capacitance - 87* - pf v ds = 25v, f = 1.0mhz operating supply voltages and current (operating conditions, unless otherwise speci?ed, v ss = 0v,v ll = +3.3v, v dd = +12v, v pp -v pf = +12v, v nn -v nf = -12v, v pp = +100v, v nn = -100v, t a = 25c) sym parameter min typ max units conditions v ll logic voltage reference 1.8 3.3 5.0 v --- v dd internal voltage supply 10 12 12.5 v --- v pf positive gate driver supply (v pp -12) - (v pp -10) v floating driver voltage supplies. v nf negative gate drive supply (v nn +10) - (v nn +12) v v sub ic substrate voltage v dd v pp +220 v must connect to the most positive potential of the ic. v pp positive hv supply 0 - +220 v --- v nn negative hv supply -220 - 0 v --- i ll v ll current en = low - - 250 a --- i ddq v dd current en = low - 100 - a --- i dden v dd current en = high 0.1 0.3 0.7 ma f = 0mhz v dd current at 5.0mhz - 0.5 - ma f = 5.0mhz, no loads i ppq v pp current en = low - 1.0 5.0 a --- i ppen v pp current at 5.0mhz - 56 - ma f = 5.0mhz, no loads i nnq v nn current en = low - 1.0 5.0 a --- i nnen v nn current at 5.0mhz - 56 - ma f = 5.0mhz, no loads i pfq v pf current en = low - 10 20 a --- i pfen v pf current at 5.0mhz - 12.2 - ma f = 5.0mhz, no loads i nfq v nf current en = low - 10 20 a --- i nfen v nf current at 5.0mhz - 6.4 - ma f = 5.0mhz, no loads under voltage and over temperature protection sym parameter min typ max units conditions v pull_up open drain pull-up voltage - - 5.0 v --- v uvdd v dd threshold 3.5 - 6.5 v --- v uvll v ll threshold 0.7 - 1.0 v --- v uvvf v pf , v nf threshold 3.5 - 6.5 v --- v ol_otp otp ?ag output low voltage - - 1.0 v v ll = 3.3v, otp = active, i pull-up = 1.0ma i otp max. open drain output cur - rent - 1.0 - ma v ll = 3.3v, otp = active, i pull-up = 1.0ma t otp over temperature threshold 95 110 125 c if over temperature occurs, otp low and all tx outputs will be hiz. t hys otp output reset hysteresis - 7.0 - c * guaranteed by design. ????????
4 hv739 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com output n-channel mosfet, txn sym parameter min typ max units conditions i out output saturation current 3.0 3.3 - a 1.0 load to ground r on channel resistance - 7.0 - i sd = 500ma c oss output capacitance - 87* - pf v ds = 25v, f = 1.0mhz logic inputs sym parameter min typ max units conditions v ih input logic high voltage 0.8v ll - v ll v --- v il input logic low voltage 0 - 0.2v ll v --- i ih input logic high current - - 10 a --- i il input logic low current -10 - - a --- c in input logic capacitance - - 5.0* pf --- ac electrical characteristics (operating conditions, unless otherwise speci?ed, v ss = 0v, v ll = +3.3v, v dd = +12v, v pp -v pf = +12v, v nn -v nf = -12v, v pp = +100v, v nn =-100v,t a = 25c) sym parameter min typ max units conditions f out output frequency range - - 35 mhz 100 resistor load hd2 second harmonic distortion - -35* - db t en power enable time - 70 250 s t dis power disable time - 1.0 10 s t drp delay time on rise time p-ch - 15 35 ns 2.0 resistor load (see timing diagram) t dfp delay time on fall time p-ch - 15 35 ns t drn delay time on rise time n-ch - 18 35 ns t dfn delay time on fall time n-ch - 18 35 ns t r output rise time - 50 65 ns 220pf//1.0k load t f output fall time - 50 65 ns truth table logic inputs output en pin nin txp txn 1 0 0 off off 1 1 0 on off 1 0 1 off on 1 1 1 on ? on ? 0 x x off off ? not allowed, may damage ic. * guaranteed by design. ????????
5 hv739 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com 10% pi n ni n output v nn v pp t r t f 0 10% 90% 90% switch ac test timing diagram t dr p 50% pi n nin t df p txp i ou t 0a txn 50% 50% 50% nin sub v pf v dd gref en txn v nf txp r1 r2 v ll en_pwr otp vss pin v pp v nn 0a v sub i ou t t dr p t df p p-driver n-driver level translator level translator ????????
6 hv739 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com +200v unipolar pulser -200v unipolar pulser nin sub +188 v vp f vd d +12v gref +1.8 to 5.0v logic inpu t vp p +200 v en v pp v nn pin c1 vnn txn +12v c2 c3 c5 c4 txp hv out 1 x1 vnf vsub vl l +1.8 ~ 5.0v +200 v c7 en_pwr otp over temp. vss p-drive r level translator n-drive r level translator hv739 nin sub -12v vp f vd d +12v gref +1.8 to 5.0v logic inpu t vp p en v pp v nn pin c1 vnn -200 v txn -188 v c2 c3 c4 txp hv out 1 x1 vnf vsub vl l +1.8 ~ 5.0v +12v c6 c7 en_pwr otp over temp. vss p-drive r level translator n-drive r level translator hv739 ????????
7 hv739 supertex inc . 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com pin description pin # name function 1 vdd positive internal voltage supply (+12v). 2 vll logic voltage high reference input (+3.3v). 3 gref logic voltage low reference. logic ground (0v). 4 en chip power enable hi = on, low = off. 5 pin input logic control of high voltage output p-fet, hi = on, low = off. 6 nin input logic control of high voltage output n-fet, hi = on, low = off. 7 otp open drain output for over temperature protection, low = over temp. 8 vss power supply return (0v) 9 vsub (pad) substrate is internally connected to the central thermal pad on the bottom of package. it must be connected to the most positive potential of the ic externally . 10 nc no connection. 11 vnf n-fet gate driver ?oating power supply, (v nf - v nn ) = +12v. 12 vnn negative high voltage power supply (-100v). 13 14 15 nc no connection. 16 vsub (pad) substrate is internally connected to the central thermal pad on the bottom of package. it must be connected to the most positive potential of the ic externally . 17 txn output n-fet drain (open drain output). 18 19 20 nc no connection. 21 22 txp output p-fet drain (open drain output). 23 24 25 vsub (pad) substrate is internally connected to the central thermal pad on the bottom of package. it must be connected to the most positive potential of the ic externally . 26 nc no connection. 27 vpp positive high voltage power supply (+100v). 28 29 30 vpf p-fet gate driver ?oating power supply, (v pp - v pf ) = +12v. 31 nc no connection. 32 vsub (pad) substrate is internally connected to the central thermal pad on the bottom of package. it must be connected to the most positive potential of the ic externally . ????????
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry an d specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//ww w. supertex.com ) ?2010 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 te l: 408-222-8888 www .supertex.com 8 hv739 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l .) doc.# dsfp-hv739 b052710 32-lead qfn package outline (k6) 5.00x5.00mm body, 1.00mm height (max), 0.50mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.18 4.85* 1.05 4.85* 1.05 0.50 bsc 0.30 ? 0.00 0 o nom 0.90 0.02 0.25 5.00 - 5.00 - 0.40 ? - - max 1.00 0.05 0.30 5.15* 3.55 ? 5.15* 3.55 ? 0.50 ? 0.15 14 o jedec registration mo-220, variation vhhd-6, issue k, june 2006. * this dimension is not speci?ed in the jedec drawing. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc. #: dspd-32qfnk65x5p050, version c041009 . notes: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. the inner tip of the lead may be either rounded or square. 1. 2. 3. seating plane to p v iew side v iew bottom v iew a a1 d e d2 e b e2 a3 l l1 vi ew b vi ew b 1 note 3 note 2 note 1 (index area d/2 x e/2) note 1 (index area d/2 x e/2) 1 32 32 ????????
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